(1) Field of the Invention
The present invention relates to a synchronous transfer mode/asynchronous transfer mode converting transmission path terminating apparatus.
(2) Description of the Related Art
In B-ISDN being rapidly spreading in recent years, asynchronous transfer mode (ATM) having overcome a limitation of the technique of synchronous transfer mode (STM) such as circuit mode, packet mode and the like is standardized on the recommendation of ITU-T as a data transfer technique in the next generation in order to meet various needs of the users.
With this, high-function and high-performance are required for a synchronous transfer mode (STM)/asynchronous transfer mode (ATM) converting transmission path terminating apparatus which terminates a transmission path in an SDH (Synchronous Digital Hierarchy) network complying with ATM in these years.
FIG. 68 is a block diagram showing an STM/ATM converting transmission path terminating apparatus. As shown in FIG. 68, the STM/ATM converting transmission path terminating apparatus (hereinafter, simply referred as a terminating apparatus) 1 has a receive STM processing unit 2, an ATM cell extracting unit 3, an ATM switch (an ATM-SW) 4, an ATM cell inserting unit 5, and a transmit STM processing unit 6. Incidentally, reference numeral 7 denotes a subscriber's terminal.
The receive STM processing unit 2 receives an STM signal sent from an STM transmission path, and conducts necessary processes such as to guard synchronization of the STM signal (a frame) or supervise a state of the transmission path (a fault or the like on the transmission path) on the basis of overhead information such as a section overhead (SOH), a path overhead (POH) and the like included in the STM signal. If the receive STM processing unit 2 detects out of synchronization of the STM frame, the STM/ATM converting transmission path terminating apparatus 1 generates and outputs an SEF (Severelly Errored Frame) signal representing out of synchronization.
The above STM frame has, in general, a section overhead 8, a path overhead 9 and a payload (an information field) 10 as-shown in FIG. 69(a), for example. These parts constitute one frame, and nine frames (9 Rows) are transmitted per 125.mu.sec.
In concrete, in one frame of the STM frame (at a transmission rate of 51.84 Mb/s, for example), the section overhead 8 accommodates overhead information (A1, A2, C1 and the like) in 9 rows (9 Rows).times.3 lines (3 bytes) and of 27 sorts,.the pass overhead 9 accommodates overhead information (J1, B3, C2 and the like) of 9 sorts (in 9 rows.times.1 line), and ATM cells 11 each for the subscriber's terminal 7 are appropriately mapped (accommodated) in the payload 10.
In the section overhead 8, A1 and A2 are frame pattern bytes used for synchronization of the STM frame, C1 is a byte representing an identification number of the STM frame, B1 is a byte used to supervise a code error in a regenerator section (between regenerators), E1 is a byte used to arrange voice in the regenerator section, F1 is a byte used to specify a fault in the regenerator section, and D1 through D3 are bytes used to communicate data in the regenerator section.
H1 through H3 are pointer bytes used to indicate a leading position of mapped data (position of J1 byte) in the payload 10, B2 is a byte used to supervise an error in a section, K1 is a byte used to control a switching system, K2 is a byte used to transfer a multiplex section (between terminal regenerator equipments), D4 through D12 are bytes used to communicate data in the multiplex section, Z1 and Z2 are spare bytes, and E2 is a byte used to arrange voice in the multiplex section.
On the other hand, in the path overhead 9, J1 is a byte used to supervise continuity of a path, B2 is a byte used to supervise an error of the path, C2 is a byte used to identify information of the path, G1 is a byte used to notify an error of a transmission path state, F2 is a byte for a channel used for maintenance, H4 is a byte used to identify a. frame number (i.e., to identify the lead of the ATM cell 11), and Z3 through Z5 are spare bytes.
The above ATM cell 11 has, as shown in FIG. 69(b), a format totaled 53 bytes configured with a header portion lla of 5 bytes consisting of own transfer destination information and the like and a data portion (information field) 11b of 48 bytes (384 bits). In the header portion. 11a, there are prepared various fields such as a generic flow control (GFC), a virtual path identifier (VPI), a virtual channel identifier (VCI), a payload type (PT), a cell loss priority (CLP), and a header error control (HEC).
Incidentally, the general flow control (GFC) is a field prepared to avoid collision of the ATM cell 11 send from each of the subscriber's terminal 7 on an interface. The virtual path identifier (VPI) and the virtual channel identifier (VCI) are fields in which number information used to discriminate transfer routes (VP and VC) are accommodated. The payload type (PT) is a field in which information used to discriminate whether data accommodated in the data portion 11b is user information or control information is accommodated. The cell loss priority (CLP) is a field in which information showing transfer priority as to whether the ATM cell 11 can be lost or not is accommodated. The header error control (HEC) is a field used to detect an error in the header portion 11a or synchronization of the ATM cell 11, in which a CRC (Cyclic Redundancy Check) code is written.
In FIG. 68, the ATM cell extracting unit 3 extracts the ATM cell 11 mapped in the payload 10 as described above with reference to FIG. 69(b) on the basis of the section overhead 8 and the path overhead 9 of the STM frame having been processed in the above receive STM processing unit 2. The ATM switch 4 conducts a switching process between each of the subscriber's terminals 7 and another terminating apparatus 1 based on the header unit 11a (VPI and VCI, particularly) of the ATM cell 11 extracted by the ATM cell extracting unit 3.
The ATM cell inserting unit 5 successively inserts the ATM cell 11 sent from each of the subscriber's terminals into a signal fed from the ATM switch 4. The transmit STM processing unit 6 conducts a necessary process such as to successively insert various overhead information for the section overhead 8 and the path overhead 9 into a signal (ATM cells) fed from the ATM cell inserting unit 5, thereby forming an STM frame having the format described above with reference to FIG. 69(b), and transmits the STM frame to the STM transmission path.
With the above structure, the terminating apparatus 1 can convert ATM cells 11 each from the subscriber's terminal 7 into a STM frame having a high transmission rate to transfer it at a high rate to another terminating apparatus 1, or extracts plural ATM cells 11 from a STM frame sent from another terminating apparatus 1 to transmit each of them to a corresponding subscriber's terminal apparatus 7 on the basis of the transfer destination information (VPI and VCI) in the header portion 11a.
In the terminating apparatus 1 as above, synchronization guard in a necessary number of stages is conducted on an ATM cell 11 mapped in the payload 10 of the STM frame when the ATM cell extracting unit 3 extracts the ATM cell 11. This synchronization guard is conducted irrespectively of a state of frame synchronization of the STM frame.
For this, if the receive STM processing unit 2 detects out of synchronization of the STM frame and the SEF signal is thus generated in the terminating apparatus 1 on the receiving side, the ATM extracting unit 3 judges that synchronization of the ATM cell 11 which is now being written in an internal storage (a FIFO storage, for example) has been established and has no header error. In consequence, the STM frame might be captured in the terminating apparatus 1 as it is although a signal quality of the STM frame is not assured.
If the receive STM processing unit 2 detects normally the frame pattern A1 and A2 bytes: refer to FIG. 69(b) ! of the STM frame even once (that is, the synchronization guard in one stage) after the SEF signal has been generated, an STM frame counting process inside the receive STM processing unit 2 becomes a normal operation. For this, the synchronization guarding process on the ATM cell 11 within the ATM cell extracting unit 3 becomes a normal operating state even under a state where the SEF signal is generated.
In consequence, synchronization of the ATM cell 11 is established before synchronization of the STM frame is established and generation of the SEF signal is stopped. In this case, the ATM cell 11 might be captured into the terminating apparatus 11 although a signal quality of the STM frame is not assured, as well.
In the terminating apparatus 1, if the receive STM processing unit 2 cannot normally detect pointer bytes H1 through H3 (bytes indicating a position of the J1 byte in the STM frame) included in the section overhead 8 of the STM frame or detect that a fault or the like has occurred in the STM transmission path, LOP (Loss of pointer) or a path-alarm indication signal (P-AIS) is generated. When these alarm signals are cancelled, a main signal (the STM frame) instantaneously becomes a normal signal from the alarm signal so that the ATM cell 11 is captured into the terminating apparatus 1 only if cell synchronization is established in the ATM cell extracting unit 3.
However, since the path overhead 9 while the receive STM processing unit 2 detected the first J1 byte refer to FIG. 69(b)! after cancellation of the LOP and P-AIS is not detected in an accurate position timing, the ATM cell 11 which might have a header error is captured into the terminating apparatus 1 during a period from an alarm cancel timing to detection of the first J1 byte.
In the terminating apparatus 1, the receive STM processing unit 2 next conducts, in general, a parity arithmetic operation using the B2 byte and B3 byte refer to FIG. 69(b)! included in the section overhead 8, and a result of the arithmetic operation is transferred as line far end block error information (L-FEBE) and path far end block error information (P-FEBE) which are information used for supervision in order to switch a transmission path according to a state of the STM transmission path to the terminating apparatus which is a transmission source of the STM frame through the transmission STM processing unit 6.
The process of transferring the L-FEBE and P-FEBE in the terminating apparatus 1 might transfer an erroneous result of the arithmetic operation since the STM frame is out of synchronization when the SEF signal is generated in the receive STM processing unit 2, which leads to unnecessary switching of the STM transmission path.
The above terminating apparatus 1 can also supervise and count a result of the parity arithmetic operation on any bit among the B1 byte through B3 byte in an interfacing process such as a performance monitoring or the like so as to switch the STM transmission path according to the count value. In such case, an erroneous result of the arithmetic operation might be counted since the STM frame is out of synchronization when the SEF signal is generated in the receive STM processing unit 2 so that the STM transmission path is unnecessarily switched as a result.